A new technical paper titled “Inner Gate Length Modulation of MFMIS Nanosheet FET Memory for Advanced Technology Nodes” was published by researchers at Samsung and Seoul National University.
Abstract
“This work proposes a new way of lowering the area ratio (AR) between the ferroelectric and metal-oxide-semiconductor (MOS) regions of metal-ferroelectric-metal-insulator-semiconductor (MFMIS) ferroelectric field-effect transistors (FeFETs): the inner gate length LG modulation. By leveraging the structural flexibility of nanosheet field-effect transistors (NSFETs), the areas of the MOS region were successfully increased by modulating the inner LG independently from the outer LG, achieving low AR without increasing the footprint area of the NSFETs. To validate the proposed inner LG modulated structure, three-dimensional (3D) technology computer-aided design (TCAD) simulations were conducted. The results show that reducing the outer LG by 2 nm while increasing the inner LG by 2 nm effectively reduces the AR by 18 %, enhancing the memory window (MW) by 22 %. Additionally, the inner LG modulation method enhances system-level performance, demonstrating an effective strategy for highly reliable FeFET-based embedded weight cells in advanced technology nodes.”
Find the technical paper here. September 2025.
K. M. Choi, J. Seung Woo and W. Young Choi, “Inner Gate Length Modulation of MFMIS Nanosheet FET Memory for Advanced Technology Nodes,” in IEEE Access, vol. 13, pp. 150517-150522, 2025, doi: 10.1109/ACCESS.2025.3602436.
The post Modulation of the Inner Gate Length in MFMIS NSFETs To Achieve Big Gains in Memory Window (Samsung, Seoul National Univ.) appeared first on Semiconductor Engineering.
