Direct patterning with UV cross-linking
Researchers from Ulsan National Institute of Science and Technology (UNIST), Yonsei University, Sungkyunkwan University, University of Chemistry and Technology Prague, and Sogang University developed a technique that enables the direct patterning of 2D semiconductor materials onto substrates without the use of toxic solvents.
The process involves dispersing 2D nanomaterials and a specially designed azide cross-linker in an isopropanol alcohol-based solvent. Once the pattern is defined on the substrate, the cross-linker is cured via exposure to UV light, solidifying the circuit pattern. Water is used to wash away unreacted cross-linker, leaving behind a clean, well-defined 2D semiconductor circuit.
The team used the technique to fabricate molybdenum disulfide (MoS2) transistors exhibiting a charge carrier mobility of 20.2 cm²/V·s, a threshold voltage of 2.0 V, and an on/off ratio of 2.7 million. An array of 49 transistors demonstrated stable operation over more than 60 days without performance degradation. The researchers were also able to successfully pattern both p-type and n-type 2D semiconductors on a single substrate to create logic circuits, including NOT, NAND, NOR gates, as well as SRAM.
“This study extends UV cross-linking technology—originally used in quantum dot displays—to 2D semiconductor materials, marking a significant step toward environmentally friendly, high-precision patterning of sensitive nanoscale devices,” said BongSoo Kim, a professor in the Department of Chemistry at UNIST, in a press release. “We believe this approach will play a crucial role in developing next-generation, energy-efficient, high-speed semiconductor chips.” [1]
2D gate stack roadmap
Researchers from Seoul National University outline a roadmap for the development of 2D semiconductor gate stacks, proposing guidelines for practical implementation and addressing essential factors such as BEOL process compatibility, low-temperature deposition below 400°C, wafer-wide uniformity, and long-term reliability.
They classified gate stack formation methods into five categories, and evaluated them against key performance metrics, including interface defects, oxide film thickness, leakage current, threshold voltage, and operating voltage. The formation methods they identified were van der Waals (vdW) dielectric, naturally oxidized dielectric, crystalline dielectric transfer method (quasi-vdW), high-κ dielectric formation using a seed layer (vdW-seeded), and those compatible with conventional processes (non-vdW-seeded). The team also noted the potential of gate stacks incorporating ferroelectric materials.
“The biggest obstacle to the commercialization of 2D transistors is the implementation of high-quality gate stacks,” said Chul-Ho Lee, a professor in the Department of Electrical and Computer Engineering at Seoul National University, in a statement. “This study provides a standard blueprint to overcome that challenge, which has significant academic and industrial implications. Moving forward, we plan to actively expand research on actual device integration and commercialization through industry–academia collaboration.” [2]
2D flash memory integration
Researchers from Fudan University integrated a 2D NOR flash memory device with a mature silicon-based CMOS technology using high-density monolithic interconnection technology for communication between different modules.
The chip supports 8-bit instruction operations, 32-bit high-speed parallel operations, and random access using a 5 MHz clock. It also demonstrated 20 ns operation and 0.644 pJ per bit energy consumption.
The team completed tape-out and achieved a memory cell yield of 94.3% by addressing random stress resulting from random roughness of the CMOS circuitry and damage from conventional chip packaging. They plan to set up a pilot production line with the goal of reaching megabyte scale within the next three to five years. [3]
References
[1] I. C. Kwak, S.-J. Kim, W. H. Cho, et al. Direct Photopatterning of Green Solvent-Processed 2D Nanomaterials for Wafer-Scale Electronics. Adv. Mater. 37, no. 40 (2025): e05917. https://doi.org/10.1002/adma.202505917
[2] Y.H. Kim, D. Lee, W. Huh, et al. Gate stack engineering of two-dimensional transistors. Nat Electron 8, 770–783 (2025). https://doi.org/10.1038/s41928-025-01448-5
[3] C. Liu, Y. Jiang, B. Shen, et al. A full-featured 2D flash chip enabled by system integration. Nature (2025). https://doi.org/10.1038/s41586-025-09621-8
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