A new technical paper titled “Beyond Backside Power: Backside Signal Routing as Technology Booster for Standard Cell Scaling” was published by researchers from University of Texas at Austin and Intel.
Abstract
“Advances in process technology enabling backside metals and contacts offer new Design-Technology Co-Optimization (DTCO) opportunities to further enhance power, performance, and area gains (PPA) in sub-3nm nodes. This work exploits backside contact technology within standard cells to extend both signal and clock routing to backside metal layers, enabling standard-cell height reduction options. We design electrically equivalent standard cells with multiple layout variants based on front versus backside pin access, achieving a 2-M0-track height reduction in 3nm Gate-All-Around Field-Effect Transistor (GAAFET) technology. Experimental evaluation across representative industrial benchmarks — including high-performance CPUs, GPUs, and general-purpose SoCs demonstrates significant benefits. Cell height reduction delivers up to 35% area savings and 10–15% total power reduction for GPU and GP-SoC designs. For high-performance CPUs, maximum performance improves by 15% at iso-power compared to backside-power using buried power rails (BSBPR). Incorporating backside signal routing with cell height reduction also reduces worst-case IR-drop by 32% relative to BSBPR. These results show that backside clock and signal routing represent the next phase of technology innovation beyond backside power delivery, enabling continued standard-cell scaling, improved intra- and inter-cell routability, and generational PPA gains while maintaining similar core transistor geometries in sub-3nm technologies.”
Find the technical paper here. October 2025.
A. A. Kedilaya et al., “Beyond Backside Power: Backside Signal Routing as Technology Booster for Standard Cell Scaling,” in IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, doi: 10.1109/JXCDC.2025.3617784. Creative commons license.
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