Experts at the Table: Semiconductor Engineering sat down to discuss progress and remaining challenges for designing with chiplets with Mark Kuemerle, vice president of technology for Marvell; Letizia Giuliano, vice president for product marketing and management at Alphawave Semi; Hee-Soo Lee, HSD segment lead for Keysight; Mick Posner, senior product group director for Cadence’s Compute Solutions Group; and Rob Kruger, product management director for Synopsys’ multi-die strategy solutions group. What follows are excerpts from a roundtable discussion held at this year’s Design Automation Conference. Part one of this discussion can be found here.
SE: One of the big selling points of soft IP was that companies didn’t have to specialize in everything. That significantly improved productivity, allowing each company to concentrate on their own secret sauce. Presumably, the same is true for chiplets. Today, you use chiplets because you have to, but eventually companies will use chiplets because it would be stupid not to. That would allow the chiplet creator to focus on one problem, become a true expert in that function, and do it much better than anybody else. How big an advantage is that ultimately going to be?
Giuliano: The division of application-specific chiplets is key. If we are able to segregate the system in the right way — and this is where customers need help today — then it becomes possible to separate out the pieces where they can do better, and to leave the rest of the problem to us. Where do you divide the system? It’s going to be I/O, a memory subsystem, a compute subsystem. We try to segregate where it makes sense. We can share the problems and use our resources to do better with that portion. We think we can do better, because if you think about I/Os and connectivity, there are so many problems to solve. How we route I/Os on a package, how we connect to the silicon interposer for 2.5D — those are big, complex problems to solve, and we have dedicated resources to do it. Today, some customers don’t know how to integrate it because they haven’t done it before. We were doing chiplets before anyone else, and we had all the ingredients to do it. Now, we want to give those ingredients to people who are used to doing it all themselves. Some applications will need that before others. We need to provide more tools to those engineers to get the things they want. We’re giving them those tools and capabilities.
Kuemerle: You said tools, and that really struck me. From an EDA enablement point of view, one of the observations I’ve had over the years is that when we were going to build chiplet-based systems in the past, it was a big deal. All the thought involved in making these things work together was really complicated. One of the key changes that I’ve seen over the last year is that standards and EDA capabilities have really advanced. A lot of the biggest challenges in building chiplets have improved. We talk a lot about the LEGO problem, but frankly, the LEGO problem is the easy problem to solve. We can solve a LEGO puzzle with a bunch of architects and engineers in a couple days, come to something we agree on with a customer, shake hands, and move down the road. Then the DFT guys get together and, back in the day, it was months later when they would return a total holistic package-level DFT solution. One thing that I’ve noticed is the ability to coordinate test amongst multiple chiplets has dramatically improved with evolving standards, along with the ability to control multiple different devices as if they’re part of the same family. That has been one of the key challenges, and I’m glad to see movement in a direction that is solving that.
Giuliano: We should replace the word chiplet marketplace with chiplet ecosystem, because it’s not just about finding a chiplet that you buy and integrate. It’s all the infrastructure.
Kuemerle: It’s all the stuff that ties it together.
Giuliano: I have a UCIe infrastructure. I have a tool and design infrastructure, so it’s not just a marketplace in 10 years. We need an ecosystem that enables you to build chiplet-based systems.
Posner: We are often asked, ‘Why would a customer take on the extra complexity of multi-die and chiplet design, and what are those barriers?’ They take it on because they want the three Cs. Cost — they are looking for efficiency, maybe switching nodes, flexibility, disaggregation, aggregation. Customization — they want to enable customization. They want something that they can mix and match and scale. Configure — they want to be able to configure it and re-use it in the future. The ecosystem, EDA tools, and IP are essential. If we look at some of the demos on the DAC floor, you’ll see, it’s no longer PowerPoint. It’s actual tools.
Kruger: We are selling collections of IPs into a chiplet space. Now you’re adding more value by building subsystems. Customers come to you for one thing, then you show them that we can do more and you don’t have to worry about this aspect, like DFT. They get to market faster. They can think about their critical problems, not the I/O problems, for example, and keep moving up the chain further. You can go from subsystems to even a soft chiplet. Maybe it’s not one-size-fits-all, but they have the flexibility to customize that, and they can do it, or we can help them. And there are different ways to do that, different partnerships, and the ecosystem. It doesn’t have to all be us. It could be with partners.
Lee: Another point is credibility. When you design your chiplets, you must be able to predict performance. This involves not just the physical implementation, but how efficiently you’ll be able to predict the performance of this when integrated into a complicated system. How are you going to measure it? When we talk about the ecosystem, it is not only an EDA perspective. It involves the entire workflow. For performance, you have to think in terms of how you measure it, where you are going to access it. We think this will impact the design of chiplets.
SE: Another thing the soft IP industry had to agree on was the list of deliverables. You don’t just say, ‘Here is your chiplet, go integrate it.’ With 2.5D integration there are new issues such as thermal, electromagnetic interference, stress, and others. What models have to go along with a chiplet to enable integration?
Kuemerle: You hit on one where we’re not making any progress at all — thermal. How do we exchange data from a thermal point of view? It’s one of the key areas where we can get into the biggest trouble. We might assume that an I/O chiplet has a uniform thermal density, but in reality it has a bunch of SerDes ports. That means hot spots, and we should know where they are. How do we share where those hot spots are? How do we make sure everybody has the data that is needed? There is no agreement about a thermal information exchange vehicle. Similarly, there is no standard footprint for a given type of IP. Every chiplet has tendrils that go into the other chips in the system. We now have an interface that 40% of the people in the industry agree upon. Sorry, I was trying to be generous. This is why we’re seeing the chiplets wagging the dog. You figure out what those tendrils are, build them into your system. You figure out what models you have for thermal and build your system around those, or play with what you can get, versus knowing that when I buy a chiplet, I know exactly what I’m going to get.
Giuliano: Plus, we have the Wild West of packaging. That is a closed system. It’s not open at all. There is the TSMC ecosystem, there is a Samsung ecosystem, another player there, and they each have a different set of collateral. Design rules are not standardized.
Posner: There is no way to send a die from one foundry to another for packaging.
Giuliano: That is a supply chain issue. You might think with HBM as the first chiplet ever, those things were resolved, but no. It is not open to everyone.
Kruger: There is so much innovation. I saw a CNN article on advanced packaging. I never thought I would see that.
Giuliano: It’s becoming a common topic across France, too.
Kuemerle: Those of us with gray hair can remember when packaging was just, you got the chip done, and then threw it to the packaging guys, and said, ‘You have two weeks. Go. Make it fit my chip. I’m not changing anything.’
Giuliano: Now the package guys are my best friend.
Kuemerle: Now they run the show.
Posner: Cadence is taking a slightly different view. There’s a lot of work that can be done to predict the deliverables you need in the future. Cadence did a tape-out of a chiplet last year for a very specific application — physical AI. It was done with the mindset that nobody is going to get into this until they have confidence in taking a deliverable from you, and that means we have to be able to take that deliverable ourself. We did this prototype tape-out, which solved a number of the challenges about how the packaging is going to work. What’s the thermal going to look like? But with Arm CSA, imec, UCIe, they all solve a little part of the chiplet solution. You’ve got an infrastructure that adheres to Arm CSA, it covers imec for security and safety, and is a mixture of hardware, electrical and software. That prototype was to prove out a chiplet ecosystem. The vision is to enable a chiplet ecosystem, and fundamentally you’ve got to create that ecosystem. The framework needs to encapsulate UCIe, chiplet management, security, safety. Cadence looked at all of the standards and tried to create a superset to jump-start that. So, when can you buy a chiplet? You can place your order with Cadence now — if you would like a physical AI solution. When you look at who’s implementing physical AI, it’s automotive OEMs who don’t traditionally have strength in semiconductor design. It’s new robotics companies, new drone companies, aerospace and defense. They are the prime example of wanting to aggregate and re-use. Cadence picked a vertical segment to jump-start an ecosystem. We want to jump-start the whole ecosystem by extending that framework, hardware, software, protocols, the EDA flow, the IP incorporation.
Lee: You talked about models. When looking at the physical implementation of chiplets, there are many challenges. We have concentrated on cases that involve using the silicon in terms of making the interconnects. Each piece of silicon is structured in a different way — for example, the transmission line structures. Is that a traditional transmission line, because we are making hatched ground planes for those transmission line structures? This is very computationally expensive to analyze. In some cases, it could take a week to get the modeling of those interconnects done. The EDA industry can help by improving interconnect-level analysis, increasing the predictability of them — especially where we see a lot of hatched ground planes. This is not just in physical implementations, but being able to predict performance, not using highly computationally expensive solutions. This is an example of how the industry is looking to EDA vendors to solve these problems. No one wants to design anything by hope. They want to validate it. But they also don’t want to spend a month running the analysis and simulations.
In the next part of this discussion, the experts talk about the potential role for a standards organization to bring the ecosystems together.
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